The GT Synthesis Trilogy
The trilogy progresses from optimizing a given PDBF, to revealing hidden PDBFs in RTL, to recognizing partial definition as a native property of sequential logic.
Question: Can the Boolean function itself be optimized before the circuit?
A PDBF represents a family of Fully Defined Boolean Functions. Completion Optimization searches the Opportunity Space and selects Legal Completions according to gate count, depth, fan-out, area, power, wiring, or another objective.
Question: Can a block that looks fully specified become partially defined inside a complete RTL design?
Yes. Surrounding circuitry prevents many local input terms from occurring. Contextual PDBF extraction preserves reachable local behavior and exposes all other local terms as hidden contextual don’t-cares.
Question: Why do sequential systems inherently contain PDBFs?
Only reachable state/input combinations determine observable behavior. The unreachable region is intrinsically unspecified and forms a Native Sequential Device PDBF.
Question: What circuit structures become available when synthesis is constrained directly by semantic care-domain compatibility?
Paper IV studies direct semantic synthesis across processor-control and protocol-oriented benchmarks and evaluates gates, depth, wiring, and fan-out under independent care-domain verification.
